Biography

Zhenxiong Chen (陈震雄) is a computer science student currently pursuing his Bachelor’s degree in Computer Science and Technology (Excellence Engineer Program) at Wuhan University (2022-2026). He specializes in operating systems, computer architecture, embedded systems, and compiler implementation, with research interests including kernel development, hardware-software co-design, system optimization, and compiler optimization techniques.

Projects

Operating System Kernels

SC7: Lightweight OS Kernel for LoongArch and RISC-V Architectures
National Second Prize, 2025 Computer System Development Capability Competition - OS Kernel Implementation Track

A 64-bit operating system kernel designed for both LoongArch and RISC-V architectures, featuring modular design for cross-platform compatibility. My main responsibilities included the file system, process management, hardware abstraction layer, signal handling, and related system calls. I designed the VFS and HSAI layers (for unified hardware abstraction), implemented and improved the underlying file system (including porting and optimizing lwext4), and integrated cache optimizations. I also designed a process-thread separation model, implemented futex and thread-level signal handling. The kernel now passes most competition test cases and can run parts of git, vim, gcc, and rustc.
Open Source Repository

PintOS Teaching Operating System Design

Invited by my advisor, I selected OS lab projects for students and, to improve my own kernel programming skills, completed the UC Berkeley CS162 PintOS project, including thread management and synchronization, user program loading and system call handling, virtual memory management, and file system implementation. As a teaching assistant, I independently designed Beamer slides for lectures. This project deepened my understanding of OS principles and gave me comprehensive kernel development and optimization experience.
Open Source Repository

Compiler Implementation

SysY2022 Compiler for RISC-V Architecture
National Second Prize, 2025 Computer System Development Capability Competition - Compiler System Implementation Track

A complete compiler implementation for the SysY2022 language targeting RISC-V architecture. The compiler features a three-phase design: frontend parsing using ANTLR4, middle-end optimizations with LLVM-inspired IR, and backend code generation with advanced optimizations. Key technical achievements include:

Frontend: ANTLR4-based parser for SysY2022 language specification
Middle-end: Comprehensive optimization passes including constant folding, dead code elimination, loop optimizations, and global value numbering
Backend: RISC-V code generation with register allocation using graph coloring, instruction scheduling, and peephole optimizations
Advanced Features: Alias analysis, scalar evolution analysis, hot-cold block analysis, and function inlining

The compiler implements over 40 optimization passes and successfully handles complex language features including multi-dimensional arrays, function calls, and control flow constructs.
Open Source Repository

Hardware Interaction

RT-Thread 5.1.0 RISC-V FPGA Porting and Image Processing Application

Invited by faculty, I independently ported the open-source RT-Thread 5.1.0 real-time OS to a RISC-V soft-core on the NEXYS A7 FPGA board, providing a multi-threaded scheduler and command-line terminal (FinSH) for embedded course experiments. I also developed an image processing demo. This project successfully established an RT-Thread environment on FPGA and has been adopted as the embedded experiment platform at Wuhan University.
Open Source Repository

RISC-V Five-Stage Pipeline CPU Design

To better understand computer architecture, I designed a five-stage RISC-V pipelined CPU supporting hazard detection, and successfully ran programs such as bubble sort on it. This project was selected as demonstration code for computer architecture labs.
Open Source Repository

Accomplishments

National Scholarship
Wuhan University First-Class Scholarship
“Sanhao” Student (Three-Good Student)
National Second Prize, OS Kernel Implementation Track, 2025 Computer System Development Capability Competition
National Second Prize, Compiler System Implementation Track, 2025 Computer System Development Capability Competition
National Second Prize, Intelligent System Innovation Design Track, 2025 Computer System Development Capability Competition
National Second Prize, Intelligent System Innovation Design Track, 2024 Computer System Development Capability Competition
National Third Prize, Artificial Intelligence Application, 2024 Chinese Collegiate Computing Competition

Teaching Experience

Digital Logic Teaching Assistant (2023-2024) - Awarded “Outstanding TA Model”
Computer Organization and Design Teaching Assistant (2023-2024) - Awarded “Outstanding TA”
Operating Systems Teaching Assistant (2024-2025) - Awarded “Outstanding TA”

Leadership and Service

Student Leadership

2023-2024: Head of News and Publicity Department, School of Computer Science, Wuhan University
2022–Present: Study Committee Member, Class of 2022 Excellence Engineer Program, School of Computer Science, Wuhan University
2025: Freshman Class Assistant for Computer Science Class 3, Grade 2025, Wuhan University
Party Work: Publicity Committee Member, 6th Party Branch, School of Computer Science, Wuhan University

Honors and Recognition

Excellent Communist Youth League Cadre
Excellent Officer
Active Participant in Social Activities
Excellent Communist Youth League Member

Zhenxiong Chen